diff options
author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
---|---|---|
committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
tree | 91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/register_file_reg.v | |
parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip |
restructured project
Diffstat (limited to 'rtl/src/register_file_reg.v')
-rw-r--r-- | rtl/src/register_file_reg.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/rtl/src/register_file_reg.v b/rtl/src/register_file_reg.v new file mode 100644 index 0000000..b1bd4fc --- /dev/null +++ b/rtl/src/register_file_reg.v @@ -0,0 +1,22 @@ +module register_file_reg ( + input clk, + input rstn, + + input [31:0] rd1_in, + input [31:0] rd2_in, + + output reg [31:0] rd1_buf, + output reg [31:0] rd2_buf +); + +always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + rd1_buf <= 32'b0; + rd2_buf <= 32'b0; + end else begin + rd1_buf <= rd1_in; + rd2_buf <= rd2_in; + end +end + +endmodule |