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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
| commit | c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 (patch) | |
| tree | a000085f4ce8d6dec3e90ecc230642eeb77d960f /rtl/src/register_file.v | |
| parent | ee94c97e4f8208d0c7404887cda16d00f67c6f1f (diff) | |
| download | riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.tar.gz riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.zip | |
align
Diffstat (limited to 'rtl/src/register_file.v')
| -rw-r--r-- | rtl/src/register_file.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/rtl/src/register_file.v b/rtl/src/register_file.v index ad3f5fe..550484d 100644 --- a/rtl/src/register_file.v +++ b/rtl/src/register_file.v @@ -2,15 +2,15 @@ // Registers of the cpu. module register_file ( - input clk, - input rstn, + input clk, + input rstn, - input we, - input [4:0] ra1, - input [4:0] ra2, - input [4:0] wa3, + input we, + input [4:0] ra1, + input [4:0] ra2, + input [4:0] wa3, - input [31:0] wd3, + input [31:0] wd3, output [31:0] rd1, output [31:0] rd2 |