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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
commitcb0be9e2039569ee7d18657e8f675d1f8369b407 (patch)
tree91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/memory_interface.v
parent98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff)
downloadriscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz
riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip
restructured project
Diffstat (limited to 'rtl/src/memory_interface.v')
-rw-r--r--rtl/src/memory_interface.v84
1 files changed, 84 insertions, 0 deletions
diff --git a/rtl/src/memory_interface.v b/rtl/src/memory_interface.v
new file mode 100644
index 0000000..09f05cb
--- /dev/null
+++ b/rtl/src/memory_interface.v
@@ -0,0 +1,84 @@
+module memory_interface (
+ input clk,
+ input rstn,
+
+ input we,
+ input [31:0] addr,
+ input [31:0] wd,
+
+ output reg [31:0] rd,
+
+ input [31:0] io_in,
+ output [31:0] io_out
+);
+
+`include "include/consts.vh"
+
+reg ram_we;
+reg io_we;
+wire [31:0] ram_rd, rom_rd;
+reg [31:0] rel_addr;
+
+ram #(.N(32), .SIZE(1024)) ram(
+ .clk(clk),
+ .rstn(rstn),
+ .we(ram_we),
+ .addr(rel_addr),
+ .data_read(ram_rd),
+ .data_write(wd)
+);
+
+rom #(.N(32), .SIZE(1024), .ROM_FILE("../../build/rom.hex")) rom(
+ .clk(clk),
+ .addr(rel_addr),
+ .data_read(rom_rd)
+);
+
+io io(
+ .clk(clk),
+ .rstn(rstn),
+ .we(io_we),
+ .addr(rel_addr),
+ .rd(io_rd),
+ .wd(wd),
+ .io_in(io_in),
+ .io_out(io_out)
+);
+
+
+// 0000 0000 Reserved
+// 0000 FFFF
+//
+// 0001 0000 ROM
+// 000F FFFF
+//
+// 0010 0000 RAM
+// FF0F FFFF
+//
+// FF10 0000 Reserved
+// FFFF FFFF
+
+
+always @ (*) begin
+ rd = 0;
+ rel_addr = 0;
+ ram_we = 0;
+ io_we = 0;
+ if ( addr >= ROM_BEGIN && addr <= ROM_END) begin
+ rd = rom_rd;
+ rel_addr = addr - ROM_BEGIN;
+ end else if (addr >= RAM_BEGIN && addr <= RAM_END) begin
+ ram_we = we;
+ rd = ram_rd;
+ rel_addr = addr - RAM_BEGIN;
+ end else if (addr >= IO_BEGIN && addr <= IO_END) begin
+ io_we = we;
+ rd = io_rd;
+ rel_addr = addr - IO_BEGIN;
+ end else begin
+ rd = 0;
+ rel_addr = 0;
+ end
+end
+
+endmodule