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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
tree | 91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/mem_addr_src_mux.v | |
parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip |
restructured project
Diffstat (limited to 'rtl/src/mem_addr_src_mux.v')
-rw-r--r-- | rtl/src/mem_addr_src_mux.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/rtl/src/mem_addr_src_mux.v b/rtl/src/mem_addr_src_mux.v new file mode 100644 index 0000000..1f34fe1 --- /dev/null +++ b/rtl/src/mem_addr_src_mux.v @@ -0,0 +1,20 @@ +module mem_addr_src_mux ( + input [31:0] src_pc, + input [31:0] src_result, + + input mem_addr_src, + + output reg [31:0] mem_addr +); + +`include "include/consts.vh" + +always @(*) begin + case (mem_addr_src) + MEM_ADDR_SRC_PC: mem_addr = src_pc; + MEM_ADDR_SRC_RESULT: mem_addr = src_result; + default: mem_addr = 32'b0; + endcase +end + +endmodule |