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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
tree | 91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/instruction_reg.v | |
parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip |
restructured project
Diffstat (limited to 'rtl/src/instruction_reg.v')
-rw-r--r-- | rtl/src/instruction_reg.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/rtl/src/instruction_reg.v b/rtl/src/instruction_reg.v new file mode 100644 index 0000000..d98ab6d --- /dev/null +++ b/rtl/src/instruction_reg.v @@ -0,0 +1,20 @@ +module instruction_reg ( + input clk, + input rstn, + + input we, + input [31:0] pc_in, instr_in, + output reg [31:0] pc_buf, instr +); + +always @ (posedge clk or negedge rstn) begin + if (!rstn) begin + pc_buf <= 32'b0; + instr <= 32'b0; + end else if (we) begin + pc_buf <= pc_in; + instr <= instr_in; + end +end + +endmodule |