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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
| commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
| tree | 91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/data_reg.v | |
| parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
| download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip | |
restructured project
Diffstat (limited to 'rtl/src/data_reg.v')
| -rw-r--r-- | rtl/src/data_reg.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/rtl/src/data_reg.v b/rtl/src/data_reg.v new file mode 100644 index 0000000..473d50a --- /dev/null +++ b/rtl/src/data_reg.v @@ -0,0 +1,14 @@ +module data_reg ( + input clk, + input rstn, + + input [31:0] data_in, + output reg [31:0] data_buf +); + +always @ (posedge clk or negedge rstn) begin + if (!rstn) data_buf <= 32'b0; + else data_buf <= data_in; +end + +endmodule |