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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
| commit | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (patch) | |
| tree | b8831bc5ad48d3375a5b05d6d532e2b3e0f2e490 /prog/src/prog.s | |
| parent | deb7d0a6fc76d5250c238d479cf97d4755abef01 (diff) | |
| download | riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.tar.gz riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.zip | |
refactoring, runs now on fpga
Diffstat (limited to 'prog/src/prog.s')
| -rw-r--r-- | prog/src/prog.s | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/prog/src/prog.s b/prog/src/prog.s index 8f23632..128af52 100644 --- a/prog/src/prog.s +++ b/prog/src/prog.s @@ -2,10 +2,15 @@ .globl _start _start: - - addi t0, zero, 3 - addi t1, zero, 5 - add t2, t0, t1 + + + addi t0, zero, 31 +reset_loop: + addi t6, zero, 0 +loop: + addi t6, t6, 1 + beq t6, t0, reset_loop + j loop halt_loop: |