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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
| commit | d107f7e40f02a7374b8685ba310500a6c38d43b1 (patch) | |
| tree | 55615eaface31b2473be3dae90fe822c5373f492 /include/consts.vh | |
| parent | 48b36fddef862c3cd5efbdd3ed3e86b179ac117b (diff) | |
| download | riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.tar.gz riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.zip | |
bug fixes
Diffstat (limited to 'include/consts.vh')
| -rw-r--r-- | include/consts.vh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/include/consts.vh b/include/consts.vh index 8c31c7d..952b0de 100644 --- a/include/consts.vh +++ b/include/consts.vh @@ -1,7 +1,8 @@ -parameter ALU_A_SRC_PC = 2'b00; -parameter ALU_A_SRC_PC_BUF = 2'b01; -parameter ALU_A_SRC_RD1_BUF = 2'b10; -parameter ALU_A_SRC_0 = 2'b11; +parameter ALU_A_SRC_PC = 3'b000; +parameter ALU_A_SRC_PC_BUF = 3'b001; +parameter ALU_A_SRC_RD1_BUF = 3'b010; +parameter ALU_A_SRC_RD1 = 3'b011; +parameter ALU_A_SRC_0 = 3'b100; parameter ALU_B_SRC_RD2_BUF = 2'b00; parameter ALU_B_SRC_IMM = 2'b01; |