diff options
| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 11:39:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 11:39:26 +0200 |
| commit | 407a3ff54a35cbe99ba6ac743376e9b0e9718fc1 (patch) | |
| tree | b96527b0b55bb63e21551f9a93d3c3271dd39988 /debug | |
| parent | def3f62f7f8d6b5bd4b15500c7d11935540e81da (diff) | |
| download | riscv_cpu-407a3ff54a35cbe99ba6ac743376e9b0e9718fc1.tar.gz riscv_cpu-407a3ff54a35cbe99ba6ac743376e9b0e9718fc1.zip | |
nextpnr himbaechel
Diffstat (limited to 'debug')
| -rw-r--r-- | debug/cpu.gtkw | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/debug/cpu.gtkw b/debug/cpu.gtkw index 92305c4..2b6da52 100644 --- a/debug/cpu.gtkw +++ b/debug/cpu.gtkw @@ -1,22 +1,22 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Wed May 15 06:26:49 2024 +[*] Wed May 15 13:30:34 2024 [*] [dumpfile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/build/waveform_cpu.vcd" -[dumpfile_mtime] "Wed May 15 06:25:06 2024" -[dumpfile_size] 6805714 +[dumpfile_mtime] "Wed May 15 07:27:23 2024" +[dumpfile_size] 6990688 [savefile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/debug/cpu.gtkw" -[timestart] 36861700 -[size] 1512 945 +[timestart] 2404400 +[size] 760 916 [pos] -1 -1 -*-15.000000 59800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-15.000000 2445000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] testbench_register_file. [treeopen] testbench_register_file.cpu. [treeopen] testbench_register_file.cpu.control_unit. -[sst_width] 253 -[signals_width] 390 -[sst_expanded] 1 -[sst_vpaned_height] 288 +[sst_width] 39 +[signals_width] 202 +[sst_expanded] 0 +[sst_vpaned_height] 278 @28 testbench_register_file.clk testbench_register_file.rst @@ -29,7 +29,7 @@ testbench_register_file.clk_cycle_count[31:0] testbench_register_file.cpu.control_unit.state[3:0] @28 testbench_register_file.cpu.instr_we -@22 +@23 testbench_register_file.cpu.instr[31:0] @28 testbench_register_file.cpu.control_unit.opcode[6:0] @@ -51,9 +51,7 @@ testbench_register_file.cpu.pc_we - @22 testbench_register_file.cpu.mem_addr[31:0] -@23 testbench_register_file.cpu.mem_rd[31:0] -@22 testbench_register_file.cpu.rd2_buf[31:0] @28 testbench_register_file.cpu.mem_we |