From 2a3951a25ffe28342177e29cf97125ed89ca59a4 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Wed, 1 May 2024 16:47:56 +0200 Subject: added make target for testvec generation --- README.md | 1 + 1 file changed, 1 insertion(+) (limited to 'README.md') diff --git a/README.md b/README.md index b56e854..92f2fe0 100644 --- a/README.md +++ b/README.md @@ -7,6 +7,7 @@ An attempt at building a simple RISCV CPU in verilog. * `make all` to synthesize, place and route the design and to generate the bitstream. * `make program` to upload the bitstream to the FPGA. * `make flash` to flash the bitsream to the FPGA. +* `make tests` to generate testvec files * `make simulate` to run the testbench (sim/testbench.v). * `make wave` to view the simulation in GTKWave. * `make clean` to clean build files. -- cgit v1.2.3