From 5d41601bb83859e684d28c6c6cdf093851722604 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Wed, 1 May 2024 16:57:36 +0200 Subject: fixed unsigned not recognized in verilog 2000 bug --- src/shift_unit.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/shift_unit.v b/src/shift_unit.v index eb931e2..1f2c96b 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -2,7 +2,7 @@ module shift_unit #( parameter N = 32 )( input signed [N-1:0] A, - input unsigned [N-1:0] SHAMT, + input [N-1:0] SHAMT, input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA output reg [N-1:0] RESULT ); -- cgit v1.2.3