| Branch | Commit message | Author | Age | |
|---|---|---|---|---|
| master | added ddca notes reference | Flavian Kaufmann | 14 months | |
| Age | Commit message | Author | ||
| 2024-06-28 | added ddca notes referenceHEADmaster | Flavian Kaufmann | ||
| 2024-05-23 | added course resource | Flavian Kaufmann | ||
| 2024-05-23 | added support for load and store operations of various sizes | Flavian Kaufmann | ||
| 2024-05-23 | support for lb, lh, lbu, lhu, sb, sh | Flavian Kaufmann | ||
| 2024-05-23 | reverted mem size | Flavian Kaufmann | ||
| 2024-05-23 | mem size | Flavian Kaufmann | ||
| 2024-05-23 | align | Flavian Kaufmann | ||
| 2024-05-21 | comments | Flavian Kaufmann | ||
| 2024-05-21 | test prog | Flavian Kaufmann | ||
| 2024-05-21 | restructured project | Flavian Kaufmann | ||
| [...] | ||||
| Clone | ||||
| https://git.flaviankaufmann.ch/riscv_cpu.git | ||||
| git@flaviankaufmann.ch:public/riscv_cpu.git | ||||
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index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |