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riscv_cpu.git
master
Simple RISC-V CPU written in Verilog
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sim
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gentestvec
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src
Mode
Name
Size
-rw-r--r--
alu.c
2571
log
plain
-rw-r--r--
cpu.c
132
log
plain
-rw-r--r--
register_file.c
1347
log
plain
