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riscv_cpu.git
master
Simple RISC-V CPU written in Verilog
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path:
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prog
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src
Mode
Name
Size
-rw-r--r--
main.c
317
log
plain
-rw-r--r--
prog.s
1213
log
plain
-rw-r--r--
startup.s
1062
log
plain
