| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | .gitignore | 6 | logplain |
| -rw-r--r-- | Makefile | 3769 | logplain |
| -rw-r--r-- | README.md | 710 | logplain |
| d--------- | cst | 42 | logplain |
| d--------- | genrom | 36 | logplain |
| d--------- | gentestvec | 98 | logplain |
| d--------- | include | 35 | logplain |
| d--------- | rom | 35 | logplain |
| d--------- | sim | 96 | logplain |
| d--------- | src | 417 | logplain |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |