| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-13 | refactored fsm output logic | Flavian Kaufmann |
| 2024-05-13 | refactoring constants | Flavian Kaufmann |
| 2024-05-13 | async reset | Flavian Kaufmann |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann |
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann |
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann |
| 2024-05-09 | added jalr instruction | Flavian Kaufmann |
| 2024-05-08 | build assembly files | Flavian Kaufmann |
| 2024-05-08 | fixed bug where register addresses were used instead of data | Flavian Kaufmann |
| 2024-05-08 | assemble simple rom | Flavian Kaufmann |
| 2024-05-08 | alu op decode | Flavian Kaufmann |
| 2024-05-07 | alu equal | Flavian Kaufmann |
| 2024-05-07 | control unit | Flavian Kaufmann |
| 2024-05-07 | cpu | Flavian Kaufmann |
| 2024-05-06 | added cpu | Flavian Kaufmann |
| 2024-05-05 | genrom | Flavian Kaufmann |
| 2024-05-05 | initialize rom to rom/rom.hex | Flavian Kaufmann |
| 2024-05-05 | added memory unit | Flavian Kaufmann |
| 2024-05-05 | register file testbench | Flavian Kaufmann |
| 2024-05-05 | added register file | Flavian Kaufmann |
| 2024-05-04 | renamed some signals | Flavian Kaufmann |
| 2024-05-04 | added support for multiple testbenches | Flavian Kaufmann |
| 2024-05-02 | register file | Flavian Kaufmann |
| 2024-05-01 | fixed unsigned not recognized in verilog 2000 bug | Flavian Kaufmann |
| 2024-05-01 | fixed alu bugs | Flavian Kaufmann |
| 2024-05-01 | alu | Flavian Kaufmann |
| 2024-04-27 | added clock divider | Flavian Kaufmann |
| 2024-04-27 | simulation | Flavian Kaufmann |
| 2024-04-27 | initial commit | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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