| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann | |
| 2024-05-08 | build assembly files | Flavian Kaufmann | |
| 2024-05-08 | assemble simple rom | Flavian Kaufmann | |
| 2024-05-05 | genrom | Flavian Kaufmann | |
| 2024-05-05 | initialize rom to rom/rom.hex | Flavian Kaufmann | |
| 2024-05-05 | added memory unit | Flavian Kaufmann | |
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index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |