aboutsummaryrefslogtreecommitdiff
path: root/src/rom.v
diff options
context:
space:
mode:
authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-09 10:13:14 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-09 10:13:14 +0200
commit678aef68af85c04015d8c385f6d6c60ffada7fad (patch)
treea36f8af2af4a5485a186084f9ee30fcbdb0c6586 /src/rom.v
parent89c0244b8bcd98e8dd273888a0cadc43357f79fc (diff)
downloadriscv_cpu-678aef68af85c04015d8c385f6d6c60ffada7fad.tar.gz
riscv_cpu-678aef68af85c04015d8c385f6d6c60ffada7fad.zip
fixed sw bug, where we wasn't set correctly
Diffstat (limited to 'src/rom.v')
-rw-r--r--src/rom.v6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/rom.v b/src/rom.v
index a2e12cd..8a25f46 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -4,7 +4,7 @@ module rom #(
)(
input clk,
input [log2(SIZE)-1:0] addr,
- output reg [N-1:0] data_read
+ output [N-1:0] data_read
);
`include "include/log2.vh"
@@ -15,9 +15,7 @@ initial begin
$readmemh("build/rom.hex", memory, 0, SIZE-1);
end
-always @(posedge clk) begin
- data_read <= {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
-end
+assign data_read = {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };