| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann |
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann |
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann |
| 2024-05-09 | added jalr instruction | Flavian Kaufmann |
| 2024-05-08 | build assembly files | Flavian Kaufmann |
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index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |