| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-06-28 | added ddca notes referenceHEADmaster | Flavian Kaufmann |
| 2024-05-23 | support for lb, lh, lbu, lhu, sb, sh | Flavian Kaufmann |
| 2024-05-23 | align | Flavian Kaufmann |
| 2024-05-21 | test prog | Flavian Kaufmann |
| 2024-05-20 | added some graphics | Flavian Kaufmann |
| 2024-05-20 | reset synchronizer | Flavian Kaufmann |
| 2024-05-20 | io | Flavian Kaufmann |
| 2024-05-20 | nextpnr himbaechel | Flavian Kaufmann |
| 2024-05-15 | fixed relative memory addressing bug | Flavian Kaufmann |
| 2024-05-15 | running c program | Flavian Kaufmann |
| 2024-05-14 | bug fixes | Flavian Kaufmann |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann |
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann |
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann |
| 2024-05-09 | added jalr instruction | Flavian Kaufmann |
| 2024-05-08 | build assembly files | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |