diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/alu.v | 4 | ||||
| -rw-r--r-- | src/alu_op_decode.v | 4 | ||||
| -rw-r--r-- | src/control_unit.v | 29 | ||||
| -rw-r--r-- | src/cpu.v | 5 |
4 files changed, 18 insertions, 24 deletions
@@ -2,8 +2,7 @@ module alu ( input [31:0] a, b, input [3:0] op, output reg [31:0] result, - output zero, - output equal + output zero ); wire [31:0] arithmetic_result, logic_result, shift_result; @@ -39,6 +38,5 @@ always @ (*) begin end assign zero = result == 32'b0; -assign equal = a == b; endmodule diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v index 895b952..b9db664 100644 --- a/src/alu_op_decode.v +++ b/src/alu_op_decode.v @@ -1,6 +1,6 @@ module alu_op_decode ( input [6:0] opcode, - input [1:0] alu_ctrl, + input alu_ctrl, input [2:0] funct3, input [6:0] funct7, output reg [3:0] alu_op @@ -19,7 +19,7 @@ parameter ALU_OP_ADD = 4'b0000, always @ (*) begin - if (alu_ctrl == 2'b00) alu_op <= ALU_OP_ADD; + if (alu_ctrl == 1'b1) alu_op <= ALU_OP_ADD; else case (opcode) 7'b0110011: begin // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND case (funct3) diff --git a/src/control_unit.v b/src/control_unit.v index 7ca2cb2..09129bd 100644 --- a/src/control_unit.v +++ b/src/control_unit.v @@ -4,7 +4,6 @@ module control_unit ( input [2:0] funct3, input [6:0] funct7, input alu_zero, - input alu_equal, output pc_we, output reg mem_addr_src, output reg mem_we, @@ -27,7 +26,7 @@ parameter s00_fetch = 4'h0, s08_execute_i = 4'h8, s09_jal = 4'h9, s10_jalr = 4'ha, - s11_beq = 4'hb; + s11_br = 4'hb; reg [3:0] state, next_state; @@ -46,7 +45,7 @@ always @ (*) begin 7'b0010011: next_state <= s08_execute_i; 7'b1101111: next_state <= s09_jal; 7'b1100111: next_state <= s10_jalr; - 7'b1100011: next_state <= s11_beq; + 7'b1100011: next_state <= s11_br; endcase s02_mem_addr: case(opcode) @@ -61,15 +60,15 @@ always @ (*) begin s08_execute_i: next_state <= s07_alu_wb; s09_jal: next_state <= s07_alu_wb; s10_jalr: next_state <= s07_alu_wb; - s11_beq: next_state <= s00_fetch; + s11_br: next_state <= s00_fetch; endcase end reg branch; reg pc_update; -reg [1:0] alu_ctrl; +reg alu_ctrl; -assign pc_we = (alu_zero & branch) | pc_update; +assign pc_we = ((alu_zero ^ funct3[0] ^ funct3[2]) & branch) | pc_update; always @ (*) begin @@ -84,19 +83,19 @@ always @ (*) begin instr_we = 1'b1; alu_a_src <= 2'b00; alu_b_src <= 2'b10; - alu_ctrl <= 2'b00; + alu_ctrl <= 1'b1; result_src <= 2'b10; pc_update = 1'b1; end s01_decode: begin alu_a_src <= 2'b01; alu_b_src <= 2'b01; - alu_ctrl <= 2'b00; + alu_ctrl <= 1'b1; end s02_mem_addr: begin alu_a_src <= 2'b10; alu_b_src <= 2'b01; - alu_ctrl <= 2'b00; + alu_ctrl <= 1'b1; end s03_mem_read: begin result_src <= 2'b00; @@ -114,7 +113,7 @@ always @ (*) begin s06_execute_r: begin alu_a_src <= 2'b10; alu_b_src <= 2'b00; - alu_ctrl <= 2'b10; + alu_ctrl <= 1'b0; end s07_alu_wb: begin result_src <= 2'b00; @@ -123,26 +122,26 @@ always @ (*) begin s08_execute_i: begin alu_a_src <= 2'b10; alu_b_src <= 2'b01; - alu_ctrl <= 2'b10; + alu_ctrl <= 1'b0; end s09_jal: begin alu_a_src <= 2'b01; alu_b_src <= 2'b10; - alu_ctrl <= 2'b00; + alu_ctrl <= 1'b1; result_src <= 2'b00; pc_update = 1'b1; end s10_jalr: begin alu_a_src <= 2'b10; alu_b_src <= 2'b01; - alu_ctrl <= 2'b00; + alu_ctrl <= 1'b1; result_src <= 2'b10; pc_update = 1'b1; end - s11_beq: begin + s11_br: begin alu_a_src <= 2'b10; alu_b_src <= 2'b00; - alu_ctrl <= 2'b01; + alu_ctrl <= 1'b0; result_src <= 2'b00; branch = 1'b1; end @@ -12,7 +12,6 @@ wire pc_we; wire instr_we; wire rf_we; wire alu_zero; -wire alu_equal; wire [3:0] alu_op; wire [1:0] alu_a_src; wire [1:0] alu_b_src; @@ -25,7 +24,6 @@ control_unit cu ( .funct3(funct3), .funct7(funct7), .alu_zero(alu_zero), - .alu_equal(alu_equal), .pc_we(pc_we), .mem_addr_src(mem_addr_src), .mem_we(mem_we), @@ -156,8 +154,7 @@ alu alu ( .b(b), .op(alu_op), .result(alu_result), - .zero(alu_zero), - .equal(alu_equal) + .zero(alu_zero) ); reg [31:0] result_buf; |