3 files changed, 14 insertions, 2 deletions
diff --git a/src/alu.v b/src/alu.v
index 6962129..6f9251c 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -2,7 +2,8 @@ module alu (
   input [31:0] a, b,
   input [3:0] op,
   output reg [31:0] result,
-  output zero
+  output zero,
+  output equal
 );
 
 wire [31:0] arithmetic_result, logic_result, shift_result;
@@ -38,5 +39,6 @@ always @ (*) begin
 end
 
 assign zero = result == 32'b0;
+assign equal = a == b;
 
 endmodule
diff --git a/src/control_unit.v b/src/control_unit.v
index 5d18f7a..a0d398a 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -4,6 +4,7 @@ module control_unit (
  input [2:0] funct3,
  input [6:0] funct7,
  input alu_zero,
+ input alu_equal,
  output pc_we,
  output mem_addr_src,
  output mem_we,
@@ -60,6 +61,12 @@ always @ (*) begin
     s10_beq:       next_state <= s00_fetch;
   endcase
 end
+
+wire branch;
+wire pc_update;
+
+assign pc_we = (alu_zero & branch) | pc_update;
+
 /*
 always @ (*) begin
  case(state)
diff --git a/src/cpu.v b/src/cpu.v
index 6e72c6b..c6f9f9e 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -11,6 +11,7 @@ wire pc_we;
 wire instr_we;
 wire rf_we;
 wire alu_zero;
+wire alu_equal;
 wire [3:0] alu_op;
 wire [1:0] alu_a_src;
 wire [1:0] alu_b_src;
@@ -23,6 +24,7 @@ control_unit cu (
   .funct3(funct3),
   .funct7(funct7),
   .alu_zero(alu_zero),
+  .alu_equal(alu_equal),
   .pc_we(pc_we),
   .mem_addr_src(mem_addr_src),
   .mem_we(mem_we),
@@ -153,7 +155,8 @@ alu alu (
   .b(b),
   .op(alu_op),
   .result(alu_result),
-  .zero(alu_zero)
+  .zero(alu_zero),
+  .equal(alu_equal)
 );
 
 reg [31:0] result_buf;