diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testbench_alu.v | 10 | ||||
| -rw-r--r-- | sim/testbench_register_file.v | 12 |
2 files changed, 11 insertions, 11 deletions
diff --git a/sim/testbench_alu.v b/sim/testbench_alu.v index 6403cd7..f011ed2 100644 --- a/sim/testbench_alu.v +++ b/sim/testbench_alu.v @@ -39,7 +39,7 @@ module testbench_alu(); assign exp_zero = exp_flags[0]; reg [31:0] alu_test_count, alu_error_count; - reg [103:0] alu_testvec [0:9999]; + reg [103:0] alu_testvec [0:20000]; initial begin #5; @@ -62,7 +62,7 @@ module testbench_alu(); alu_test_count = alu_test_count + 1; - if ((alu_test_count == 9027)) begin + if ((alu_test_count == 10027)) begin $display("FINISHED (ALU), with %d errors out of %d tests.", alu_error_count, alu_test_count); #16; @@ -73,9 +73,9 @@ module testbench_alu(); - alu #(.N(32)) alu ( - .src0(a), - .src1(b), + alu alu ( + .a(a), + .b(b), .op(op), .result(result), .zero(zero) diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v index 79825dc..a22f3e1 100644 --- a/sim/testbench_register_file.v +++ b/sim/testbench_register_file.v @@ -14,12 +14,12 @@ register_file uut ( .clk(clk), .rst(rst), .we(we), - .addr_read0(addr_rs0), - .addr_read1(addr_rs1), - .addr_write2(addr_rd2), - .data_read0(data_rs0), - .data_read1(data_rs1), - .data_write2(data_rd2) + .rs1(addr_rs0), + .rs2(addr_rs1), + .rd(addr_rd2), + .rs1_data(data_rs0), + .rs2_data(data_rs1), + .rd_data(data_rd2) ); integer file, r, eof; |