diff options
Diffstat (limited to 'debug/cpu.gtkw')
| -rw-r--r-- | debug/cpu.gtkw | 274 |
1 files changed, 151 insertions, 123 deletions
diff --git a/debug/cpu.gtkw b/debug/cpu.gtkw index 2b6da52..08e251b 100644 --- a/debug/cpu.gtkw +++ b/debug/cpu.gtkw @@ -1,163 +1,191 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Wed May 15 13:30:34 2024 +[*] Tue May 21 13:54:43 2024 [*] [dumpfile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/build/waveform_cpu.vcd" -[dumpfile_mtime] "Wed May 15 07:27:23 2024" -[dumpfile_size] 6990688 +[dumpfile_mtime] "Tue May 21 13:32:51 2024" +[dumpfile_size] 9041510 [savefile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/debug/cpu.gtkw" -[timestart] 2404400 -[size] 760 916 -[pos] -1 -1 -*-15.000000 2445000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] testbench_register_file. -[treeopen] testbench_register_file.cpu. -[treeopen] testbench_register_file.cpu.control_unit. -[sst_width] 39 -[signals_width] 202 -[sst_expanded] 0 +[timestart] 0 +[size] 1512 945 +[pos] -1 -2 +*-15.000000 34400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] testbench_cpu. +[treeopen] testbench_cpu.cpu. +[sst_width] 253 +[signals_width] 289 +[sst_expanded] 1 [sst_vpaned_height] 278 -@28 -testbench_register_file.clk -testbench_register_file.rst @24 -testbench_register_file.clk_cycle_count[31:0] -@200 -- -@22 -[color] 2 -testbench_register_file.cpu.control_unit.state[3:0] -@28 -testbench_register_file.cpu.instr_we -@23 -testbench_register_file.cpu.instr[31:0] +[color] 6 +testbench_cpu.clk_cycle_count[31:0] @28 -testbench_register_file.cpu.control_unit.opcode[6:0] -testbench_register_file.cpu.control_unit.funct3[2:0] -@22 -testbench_register_file.cpu.control_unit.funct7[6:0] +[color] 6 +testbench_cpu.clk +[color] 6 +testbench_cpu.rst @200 - @22 -testbench_register_file.cpu.imm[31:0] +[color] 1 +testbench_cpu.cpu.control_unit.state[3:0] @200 - +-PC @22 -testbench_register_file.cpu.pc[31:0] -testbench_register_file.cpu.pc_buf[31:0] +[color] 4 +testbench_cpu.cpu.pc[31:0] +[color] 2 +testbench_cpu.cpu.pc_buf[31:0] @28 -testbench_register_file.cpu.pc_we +[color] 5 +testbench_cpu.cpu.pc_we @200 - +-Instruction @22 -testbench_register_file.cpu.mem_addr[31:0] -testbench_register_file.cpu.mem_rd[31:0] -testbench_register_file.cpu.rd2_buf[31:0] +[color] 7 +testbench_cpu.cpu.instr[31:0] @28 -testbench_register_file.cpu.mem_we -@22 -testbench_register_file.cpu.data_buf[31:0] -@200 -- +[color] 4 +testbench_cpu.cpu.control_unit.opcode[6:0] +[color] 4 +testbench_cpu.cpu.control_unit.funct3[2:0] +[color] 4 +testbench_cpu.cpu.control_unit.funct7[6:0] @22 -[color] 5 -testbench_register_file.cpu.alu_a[31:0] -[color] 5 -testbench_register_file.cpu.alu_b[31:0] +[color] 4 +testbench_cpu.cpu.imm[31:0] @28 [color] 5 -testbench_register_file.cpu.alu_b_src[1:0] +testbench_cpu.cpu.instr_we +@200 +- +-Memory @22 -[color] 5 -testbench_register_file.cpu.alu_op[3:0] +[color] 3 +testbench_cpu.cpu.mem_addr[31:0] +[color] 4 +testbench_cpu.cpu.mem_rd[31:0] +[color] 2 +testbench_cpu.cpu.data_buf[31:0] +[color] 4 ++{testbench_cpu.cpu.mem_wd[31:0]} testbench_cpu.cpu.rd2_buf[31:0] @28 -testbench_register_file.cpu.control_unit.alu_ctrl -testbench_register_file.cpu.alu_zero -@22 [color] 5 -testbench_register_file.cpu.alu_result[31:0] +testbench_cpu.cpu.mem_we @200 - +-ALU @22 -testbench_register_file.cpu.result[31:0] +[color] 4 +testbench_cpu.cpu.alu_a[31:0] +[color] 4 +testbench_cpu.cpu.alu_b[31:0] +[color] 4 +testbench_cpu.cpu.alu_result[31:0] +[color] 2 +testbench_cpu.cpu.alu_result_buf[31:0] +@28 +[color] 5 +testbench_cpu.cpu.alu_op[3:0] @200 - +-Register File @22 [color] 3 -testbench_register_file.cpu.register_file.ra1[4:0] +testbench_cpu.cpu.ra1[4:0] [color] 3 -testbench_register_file.cpu.register_file.ra2[4:0] +testbench_cpu.cpu.ra2[4:0] [color] 3 -testbench_register_file.cpu.register_file.wa3[4:0] +testbench_cpu.cpu.wa3[4:0] +[color] 4 +testbench_cpu.cpu.rd1[31:0] +[color] 2 +testbench_cpu.cpu.rd1_buf[31:0] +[color] 4 +testbench_cpu.cpu.rd2[31:0] +[color] 2 +testbench_cpu.cpu.rd2_buf[31:0] +[color] 4 +testbench_cpu.cpu.result[31:0] @28 -[color] 3 -testbench_register_file.cpu.rf_we +[color] 5 +testbench_cpu.cpu.rf_we @200 - @22 -[color] 3 -testbench_register_file.cpu.register_file.reg_x0_zero[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x1_ra[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x2_sp[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x3_gp[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x4_tp[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x5_t0[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x6_t1[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x7_t2[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x8_s0_fp[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x9_s1[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x10_a0[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x11_a1[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x12_a2[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x13_a3[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x14_a4[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x15_a5[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x16_a6[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x17_a7[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x18_s2[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x19_s3[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x20_s4[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x21_s5[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x22_s6[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x23_s7[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x24_s8[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x25_s9[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x26_s10[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x27_s11[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x28_t3[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x29_t4[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x30_t5[31:0] -[color] 3 -testbench_register_file.cpu.register_file.reg_x31_t6[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x0_zero[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x1_ra[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x2_sp[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x3_gp[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x4_tp[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x5_t0[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x6_t1[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x7_t2[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x8_s0_fp[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x9_s1[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x10_a0[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x11_a1[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x12_a2[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x13_a3[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x14_a4[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x15_a5[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x16_a6[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x17_a7[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x18_s2[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x19_s3[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x20_s4[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x21_s5[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x22_s6[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x23_s7[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x24_s8[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x25_s9[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x26_s10[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x27_s11[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x28_t3[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x29_t4[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x30_t5[31:0] +[color] 6 +testbench_cpu.cpu.register_file.reg_x31_t6[31:0] +@200 +- +-IO +@23 +[color] 4 +testbench_cpu.cpu.io_in[31:0] +[color] 4 +testbench_cpu.cpu.io_out[31:0] [pattern_trace] 1 [pattern_trace] 0 |