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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /src/mem_addr_src_mux.v | |
parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip |
refactoring
Diffstat (limited to 'src/mem_addr_src_mux.v')
-rw-r--r-- | src/mem_addr_src_mux.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mem_addr_src_mux.v b/src/mem_addr_src_mux.v new file mode 100644 index 0000000..a415287 --- /dev/null +++ b/src/mem_addr_src_mux.v @@ -0,0 +1,15 @@ +module mem_addr_src_mux ( + input [31:0] src_pc, src_result, + input mem_addr_src, + output reg [31:0] mem_addr +); + +always @(*) begin + case (mem_addr_src) + 1'b0: mem_addr <= src_pc; + 1'b1: mem_addr <= src_result; + default: mem_addr <= 32'b0; + endcase +end + +endmodule |