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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
| commit | 9d69eaa8e3be69ead0918d915bdacb7d0def9281 (patch) | |
| tree | ba08ada6f1a0ca95ace1311d176f265139ac95b9 /src/logic_unit.v | |
| parent | f2e07b4ae7f4410efaf100e830a51d7dcb0d1b28 (diff) | |
| download | riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.tar.gz riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.zip | |
cpu
Diffstat (limited to 'src/logic_unit.v')
| -rw-r--r-- | src/logic_unit.v | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/logic_unit.v b/src/logic_unit.v index 0bbd642..f9f62a2 100644 --- a/src/logic_unit.v +++ b/src/logic_unit.v @@ -1,16 +1,15 @@ -module logic_unit #( - parameter N = 32 -)( - input [N-1:0] src0, src1, - input [1:0] op, // 00: AND, 01: OR, 10: XOR - output reg [N-1:0] result +module logic_unit ( + input [31:0] a, b, + input [1:0] op, + output reg [31:0] result ); always @ (*) begin case (op) - 2'b00: result <= src0 & src1; - 2'b01: result <= src0 | src1; - 2'b10: result <= src0 ^ src1; + 2'b00: result <= a & b; // AND + 2'b01: result <= a | b; // OR + 2'b10: result <= a ^ b; // XOR + default: result <= 32'b0; endcase end |