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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
| commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
| tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /src/data_reg.v | |
| parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
| download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip | |
refactoring
Diffstat (limited to 'src/data_reg.v')
| -rw-r--r-- | src/data_reg.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/data_reg.v b/src/data_reg.v new file mode 100644 index 0000000..f7530e2 --- /dev/null +++ b/src/data_reg.v @@ -0,0 +1,13 @@ +module data_reg ( + input clk, + input rstn, + input [31:0] data_in, + output reg [31:0] data_buf +); + +always @ (posedge clk) begin + if (!rstn) data_buf <= 32'b0; + else data_buf <= data_in; +end + +endmodule |