added register file

1 files changed, 11 insertions, 11 deletions

diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index 71255c2..59f5cae 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -1,23 +1,23 @@
 module arithmetic_unit #(
   parameter N = 32
 )(
-  input [N-1:0] au_src0, au_src1,
-  input [1:0] au_op, // 00: ADD, 01: SUB, 11: SLT
-  output [N-1:0] au_result
+  input [N-1:0] src0, src1,
+  input [1:0] op, // 00: ADD, 01: SUB, 11: SLT
+  output [N-1:0] result
 );
 
-wire [N-1:0] au_src1_inv, au_sum;
-wire au_cin, au_src0_lt_src1, au_overflow;
+wire [N-1:0] src1_inv, sum;
+wire cin, src0_lt_src1, overflow;
 
-assign au_src1_inv = au_op[0] ? ~au_src1 : au_src1;
-assign au_cin = au_op[0];
+assign src1_inv = op[0] ? ~src1 : src1;
+assign cin = op[0];
 
-assign au_sum = au_src0 + au_src1_inv + au_cin;
+assign sum = src0 + src1_inv + cin;
 
-assign au_overflow = ~(au_src0[N-1] ^ au_src1[N-1] ^ au_op[0]) & (au_src0[N-1] ^ au_sum[N-1]);
+assign overflow = ~(src0[N-1] ^ src1[N-1] ^ op[0]) & (src0[N-1] ^ sum[N-1]);
 
-assign au_src0_lt_src1 = au_overflow ^ au_sum[N-1];
+assign src0_lt_src1 = overflow ^ sum[N-1];
 
-assign au_result = au_op[1] ? {{(N-1){1'b0}}, au_src0_lt_src1} : au_sum;
+assign result = op[1] ? {{(N-1){1'b0}}, src0_lt_src1} : sum;
 
 endmodule