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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-08 11:39:56 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-08 11:39:56 +0200 |
| commit | d1133b1f41d426482cb54b747caada8427654b3a (patch) | |
| tree | 10cd12c7df707967d8ddff8d0a7d98f646e75b86 /src/alu_op_decode.v | |
| parent | aa005bc8b667668eb43c0ae62e00aefd1c3c1af5 (diff) | |
| download | riscv_cpu-d1133b1f41d426482cb54b747caada8427654b3a.tar.gz riscv_cpu-d1133b1f41d426482cb54b747caada8427654b3a.zip | |
fixed bug where register addresses were used instead of data
Diffstat (limited to 'src/alu_op_decode.v')
| -rw-r--r-- | src/alu_op_decode.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v index 8e801c8..895b952 100644 --- a/src/alu_op_decode.v +++ b/src/alu_op_decode.v @@ -19,7 +19,8 @@ parameter ALU_OP_ADD = 4'b0000, always @ (*) begin - case (opcode) + if (alu_ctrl == 2'b00) alu_op <= ALU_OP_ADD; + else case (opcode) 7'b0110011: begin // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND case (funct3) 3'b000: alu_op <= funct7[5] ? ALU_OP_SUB : ALU_OP_ADD; |