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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
| commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
| tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /src/alu_b_src_mux.v | |
| parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
| download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip | |
refactoring
Diffstat (limited to 'src/alu_b_src_mux.v')
| -rw-r--r-- | src/alu_b_src_mux.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/alu_b_src_mux.v b/src/alu_b_src_mux.v new file mode 100644 index 0000000..e7df223 --- /dev/null +++ b/src/alu_b_src_mux.v @@ -0,0 +1,16 @@ +module alu_b_src_mux ( + input [31:0] src_rd2_buf, src_imm, + input [1:0] alu_b_src, + output reg [31:0] alu_b +); + +always @(*) begin + case (alu_b_src) + 2'b00: alu_b <= src_rd2_buf; + 2'b01: alu_b <= src_imm; + 2'b10: alu_b <= 32'h4; + default: alu_b <= 32'b0; + endcase +end + +endmodule |