cpu

1 files changed, 19 insertions, 20 deletions

diff --git a/src/alu.v b/src/alu.v
index e90694b..6962129 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -1,43 +1,42 @@
-module alu #(
-  parameter N = 32
-)(
-  input [N-1:0] src0, src1,
-  input [3:0] op, // alu_op[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT 
-  output reg [N-1:0] result,
+module alu (
+  input [31:0] a, b,
+  input [3:0] op,
+  output reg [31:0] result,
   output zero
 );
 
-wire [N-1:0] arithmetic_result, logic_result, shift_result;
+wire [31:0] arithmetic_result, logic_result, shift_result;
 
-arithmetic_unit #(.N(N)) au (
-  .src0(src0),
-  .src1(src1),
+arithmetic_unit au (
+  .a(a),
+  .b(b),
   .op(op[1:0]),
   .result(arithmetic_result)
 );
 
-logic_unit #(.N(N)) lu (
-  .src0(src0),
-  .src1(src1),
+logic_unit lu (
+  .a(a),
+  .b(b),
   .op(op[1:0]),
   .result(logic_result)
 );
 
-shift_unit #(.N(N)) su (
-  .src0(src0),
-  .shamt(src1),
+shift_unit su (
+  .a(a),
+  .b(b[4:0]),
   .op(op[1:0]),
   .result(shift_result)
 );
 
 always @ (*) begin
   case (op[3:2])
-    2'b00: result <= arithmetic_result;
-    2'b01: result <= logic_result;
-    2'b10: result <= shift_result;
+    2'b00: result <= arithmetic_result; // ARITHMETIC
+    2'b01: result <= logic_result;      // LOGIC
+    2'b10: result <= shift_result;      // SHIFT
+    default: result <= 31'b0;
   endcase
 end
 
-assign zero = ~|result;
+assign zero = result == 32'b0;
 
 endmodule