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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
| commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
| tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /sim/testbench_cpu.v | |
| parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
| download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip | |
refactoring
Diffstat (limited to 'sim/testbench_cpu.v')
| -rw-r--r-- | sim/testbench_cpu.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v index 2a2e185..d6c3975 100644 --- a/sim/testbench_cpu.v +++ b/sim/testbench_cpu.v @@ -5,9 +5,9 @@ module testbench_register_file(); reg clk; reg rst; -cpu uut ( +cpu cpu ( .clk(clk), - .rst(rst) + .rstn(!rst) ); integer file, r, eof; |