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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
| commit | 9d69eaa8e3be69ead0918d915bdacb7d0def9281 (patch) | |
| tree | ba08ada6f1a0ca95ace1311d176f265139ac95b9 /sim/testbench_alu.v | |
| parent | f2e07b4ae7f4410efaf100e830a51d7dcb0d1b28 (diff) | |
| download | riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.tar.gz riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.zip | |
cpu
Diffstat (limited to 'sim/testbench_alu.v')
| -rw-r--r-- | sim/testbench_alu.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/sim/testbench_alu.v b/sim/testbench_alu.v index 6403cd7..f011ed2 100644 --- a/sim/testbench_alu.v +++ b/sim/testbench_alu.v @@ -39,7 +39,7 @@ module testbench_alu(); assign exp_zero = exp_flags[0]; reg [31:0] alu_test_count, alu_error_count; - reg [103:0] alu_testvec [0:9999]; + reg [103:0] alu_testvec [0:20000]; initial begin #5; @@ -62,7 +62,7 @@ module testbench_alu(); alu_test_count = alu_test_count + 1; - if ((alu_test_count == 9027)) begin + if ((alu_test_count == 10027)) begin $display("FINISHED (ALU), with %d errors out of %d tests.", alu_error_count, alu_test_count); #16; @@ -73,9 +73,9 @@ module testbench_alu(); - alu #(.N(32)) alu ( - .src0(a), - .src1(b), + alu alu ( + .a(a), + .b(b), .op(op), .result(result), .zero(zero) |