aboutsummaryrefslogtreecommitdiff
path: root/sim/testbench_alu.v
diff options
context:
space:
mode:
authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-01 16:47:56 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-01 16:47:56 +0200
commit2a3951a25ffe28342177e29cf97125ed89ca59a4 (patch)
treec34e152c2c734cb9f8d37da004e9af41e4126348 /sim/testbench_alu.v
parent62fec7789b516561903358a29b45bd4a6746861f (diff)
downloadriscv_cpu-2a3951a25ffe28342177e29cf97125ed89ca59a4.tar.gz
riscv_cpu-2a3951a25ffe28342177e29cf97125ed89ca59a4.zip
added make target for testvec generation
Diffstat (limited to 'sim/testbench_alu.v')
0 files changed, 0 insertions, 0 deletions