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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:47:56 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:47:56 +0200 |
| commit | 2a3951a25ffe28342177e29cf97125ed89ca59a4 (patch) | |
| tree | c34e152c2c734cb9f8d37da004e9af41e4126348 /sim/testbench.v | |
| parent | 62fec7789b516561903358a29b45bd4a6746861f (diff) | |
| download | riscv_cpu-2a3951a25ffe28342177e29cf97125ed89ca59a4.tar.gz riscv_cpu-2a3951a25ffe28342177e29cf97125ed89ca59a4.zip | |
added make target for testvec generation
Diffstat (limited to 'sim/testbench.v')
| -rw-r--r-- | sim/testbench.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/testbench.v b/sim/testbench.v index 33362d7..5a47111 100644 --- a/sim/testbench.v +++ b/sim/testbench.v @@ -25,7 +25,7 @@ module testbench(); reg [103:0] testvec [0:9999]; initial begin - $readmemh("../testvecs/alu_testvec.txt", testvec); + $readmemh("alu_testvec.txt", testvec); error_count = 0; vector_count = 0; end |