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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-09 09:00:34 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-09 09:00:34 +0200 |
| commit | 89c0244b8bcd98e8dd273888a0cadc43357f79fc (patch) | |
| tree | ba7ae6d7dca6e98cb61adcbdfcf1577bc22e1b17 /prog | |
| parent | 51e35d48453b6b12eecb97b23fb885f9ae87afe1 (diff) | |
| download | riscv_cpu-89c0244b8bcd98e8dd273888a0cadc43357f79fc.tar.gz riscv_cpu-89c0244b8bcd98e8dd273888a0cadc43357f79fc.zip | |
added jalr instruction
Diffstat (limited to 'prog')
| -rw-r--r-- | prog/src/prog.s | 45 |
1 files changed, 39 insertions, 6 deletions
diff --git a/prog/src/prog.s b/prog/src/prog.s index bbae5bb..2759554 100644 --- a/prog/src/prog.s +++ b/prog/src/prog.s @@ -2,18 +2,51 @@ .globl _start _start: - #la sp, stack_top - - #li a0, 10 - #li a1, 20 - #add a2, a0, a1 + + # testing alu +/* addi t0, zero, 5 addi t1, zero, 3 - add t2, t0, t1 + + #add t2, t0, t1 + #sub t2, t0, t1 + + xor t2, t0, t1 + or t2, t0, t1 + and t2, t0, t1 + + slt t2, t0, t1 + slt t2, t1, t0 + + addi t0, zero, -1 + + slt t2, t0, t1 + slt t2, t1, t0 + + sltu t2, t0, t1 + sltu t2, t1, t0 + + addi t0, zero, 1 + + sll t2, t0, 31 + sra t2, t2, 31 + sll t2, t0, 31 + srl t2, t2, 31 +*/ + + + jal target + addi t0, zero, 2 + + halt_loop: j halt_loop +target: + addi t0, zero, 1 + jalr zero, ra, 0 + .section .data |