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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 18:33:28 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 18:33:28 +0200 |
| commit | 59bc2fc1f75dbda7f8c36409bcf3f5198bfc3eaa (patch) | |
| tree | 85092182470cece8cbbf446d15cc513900ab6c5b /include/consts.vh | |
| parent | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (diff) | |
| download | riscv_cpu-59bc2fc1f75dbda7f8c36409bcf3f5198bfc3eaa.tar.gz riscv_cpu-59bc2fc1f75dbda7f8c36409bcf3f5198bfc3eaa.zip | |
refactored fsm output logic
Diffstat (limited to 'include/consts.vh')
| -rw-r--r-- | include/consts.vh | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/include/consts.vh b/include/consts.vh index 49133a7..8c31c7d 100644 --- a/include/consts.vh +++ b/include/consts.vh @@ -105,4 +105,15 @@ parameter FUNCT7_ALU_SRL = 7'b0000000; parameter FUNCT7_ALU_SRA = 7'b0100000; parameter ALU_CTRL_OP = 1'b0; -parameter ALU_CTRL_ADD = 1'b1;
\ No newline at end of file +parameter ALU_CTRL_ADD = 1'b1; + +parameter MEM_WE_ENABLE = 1'b1; +parameter MEM_WE_DISABLE = 1'b0; +parameter RF_WE_ENABLE = 1'b1; +parameter RF_WE_DISABLE = 1'b0; +parameter INSTR_WE_ENABLE = 1'b1; +parameter INSTR_WE_DISABLE = 1'b0; +parameter PC_UPDATE_ENABLE = 1'b1; +parameter PC_UPDATE_DISABLE = 1'b0; +parameter BRANCH_ENABLE = 1'b1; +parameter BRANCH_DISABLE = 1'b0;
\ No newline at end of file |