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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
| commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
| tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /gentestvec/gentestvec_register_file.c | |
| parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
| download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip | |
refactoring
Diffstat (limited to 'gentestvec/gentestvec_register_file.c')
| -rw-r--r-- | gentestvec/gentestvec_register_file.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gentestvec/gentestvec_register_file.c b/gentestvec/gentestvec_register_file.c index a9ff1c5..5a50d9b 100644 --- a/gentestvec/gentestvec_register_file.c +++ b/gentestvec/gentestvec_register_file.c @@ -14,9 +14,10 @@ void write_reg(uint32_t addr, uint32_t data, bool we) { void test(uint32_t addr_rs0, uint32_t addr_rs1, uint32_t addr_rd2, uint32_t data_rd2, bool we) { + + write_reg(addr_rd2, data_rd2, we); uint32_t data_rs0 = read_reg(addr_rs0); uint32_t data_rs1 = read_reg(addr_rs1); - write_reg(addr_rd2, data_rd2, we); printf("%08X_%08X__%08X_%08X__%08X_%08X_%01X\n", addr_rs0, data_rs0, addr_rs1, data_rs1, addr_rd2, data_rd2, we); } |