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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
| commit | 9d69eaa8e3be69ead0918d915bdacb7d0def9281 (patch) | |
| tree | ba08ada6f1a0ca95ace1311d176f265139ac95b9 /gentestvec/gentestvec_alu.c | |
| parent | f2e07b4ae7f4410efaf100e830a51d7dcb0d1b28 (diff) | |
| download | riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.tar.gz riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.zip | |
cpu
Diffstat (limited to 'gentestvec/gentestvec_alu.c')
| -rw-r--r-- | gentestvec/gentestvec_alu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/gentestvec/gentestvec_alu.c b/gentestvec/gentestvec_alu.c index 39de43e..4a11a74 100644 --- a/gentestvec/gentestvec_alu.c +++ b/gentestvec/gentestvec_alu.c @@ -6,7 +6,8 @@ typedef enum { ADD = 0b0000, SUB = 0b0001, - SLT = 0b0011, + SLT = 0b0010, + SLTU = 0b0011, AND = 0b0100, OR = 0b0101, @@ -31,6 +32,9 @@ void test_op(OP op, uint32_t a, uint32_t b) { case SLT: result = (int32_t)a < (int32_t)b; break; + case SLTU: + result = a < b; + break; case AND: result = a & b; @@ -79,6 +83,7 @@ int main(int argc, const char *argv[]) { test_op(SLT, 0x8fffffff, 0xffffffff); test_op(SLT, 0xffffffff, 0x00000001); test_op(SLT, 0x00000001, 0xffffffff); + test_op_random(SLTU, 1000); test_op_random(OR, 1000); test_op(OR, 0x00000000, 0x00000000); |