From ca5a25cfbdbefada9dfb94a097b65e69226f3f9a Mon Sep 17 00:00:00 2001
From: Flavian Kaufmann <flavian@flaviankaufmann.ch>
Date: Wed, 1 May 2024 16:08:53 +0200
Subject: fixed alu bugs

---
 src/alu.v             | 10 +++-------
 src/arithmetic_unit.v |  9 ++++-----
 src/shift_unit.v      | 10 +++++-----
 3 files changed, 12 insertions(+), 17 deletions(-)

(limited to 'src')

diff --git a/src/alu.v b/src/alu.v
index 61bb2fb..d54721b 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -4,8 +4,7 @@ module alu #(
   input [N-1:0] A, B,
   input [3:0] OP, // OP[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT 
   output reg [N-1:0] RESULT,
-  output ZERO,
-  output OVERFLOW
+  output ZERO
 );
 
 wire [N-1:0] arithmetic_result, logic_result, shift_result;
@@ -14,8 +13,7 @@ arithmetic_unit #(.N(N)) au (
   .A(A),
   .B(B),
   .OP(OP[1:0]),
-  .RESULT(arithmetic_result),
-  .OVERFLOW(overflow)
+  .RESULT(arithmetic_result)
 );
 
 logic_unit #(.N(N)) lu (
@@ -27,7 +25,7 @@ logic_unit #(.N(N)) lu (
 
 shift_unit #(.N(N)) su (
   .A(A),
-  .SHAMT(B[clog2(N):0]),
+  .SHAMT(B),
   .OP(OP[1:0]),
   .RESULT(shift_result)
 );
@@ -40,8 +38,6 @@ always @ (*) begin
   endcase
 end
 
-assign OVERFLOW = OP[3:2] == 2'b00 ? overflow : 0;
-
 assign ZERO = ~|RESULT;
 
 endmodule
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index be087a7..64ec0f9 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -3,21 +3,20 @@ module arithmetic_unit #(
 )(
   input [N-1:0] A, B,
   input [1:0] OP, // 00: ADD, 01: SUB, 11: SLT
-  output [N-1:0] RESULT,
-  output OVERFLOW
+  output [N-1:0] RESULT
 );
 
 wire [N-1:0] b, sum;
-wire cin, altb;
+wire cin, altb, overflow;
 
 assign b = OP[0] ? ~B : B;
 assign cin = OP[0];
 
 assign sum = A + b + cin;
 
-assign OVERFLOW = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]);
+assign overflow = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]);
 
-assign altb = OVERFLOW ^ sum[N-1];
+assign altb = overflow ^ sum[N-1];
 
 assign RESULT = OP[1] ? {{(N-1){1'b0}}, altb} : sum;
 
diff --git a/src/shift_unit.v b/src/shift_unit.v
index 55b6add..eb931e2 100644
--- a/src/shift_unit.v
+++ b/src/shift_unit.v
@@ -1,17 +1,17 @@
 module shift_unit #(
   parameter N = 32
 )(
-  input [N-1:0] A,
-  input [clog2(N):0] SHAMT,
+  input signed [N-1:0] A,
+  input unsigned [N-1:0] SHAMT,
   input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA 
   output reg [N-1:0] RESULT
 );
 
 always @ (*) begin
   case (OP)
-    2'b00: RESULT <= A << SHAMT;
-    2'b01: RESULT <= A >> SHAMT;
-    2'b11: RESULT <= A >>> SHAMT;
+    2'b00: RESULT <= A << SHAMT % N;
+    2'b01: RESULT <= A >> SHAMT % N;
+    2'b11: RESULT <= A >>> SHAMT % N;
   endcase
 end
 
-- 
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