From 7addab23add21dcb94bab5525787d1b97b11ce39 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 27 Apr 2024 14:27:10 +0200 Subject: simulation --- src/top.v | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/top.v b/src/top.v index 8dc9684..6fab4a6 100644 --- a/src/top.v +++ b/src/top.v @@ -4,18 +4,15 @@ module top ( output [5:0] led ); -reg [25:0] ctr_q; -wire [25:0] ctr_d; +reg [5:0] ctr_q; +wire [5:0] ctr_d; -// Sequential code (flip-flop) always @(posedge clk) begin - if (key) begin - ctr_q <= ctr_d; - end + if (key) ctr_q <= ctr_d; + else ctr_q <= 6'b0; end -// Combinational code (boolean logic) -assign ctr_d = ctr_q + 1'b1; -assign led = ctr_q[25:20]; +assign ctr_d = ctr_q + 6'b1; +assign led = ctr_q; endmodule -- cgit v1.2.3