From deb7d0a6fc76d5250c238d479cf97d4755abef01 Mon Sep 17 00:00:00 2001
From: Flavian Kaufmann <flavian@flaviankaufmann.ch>
Date: Sun, 12 May 2024 21:27:41 +0200
Subject: refactoring

---
 src/top.v | 34 +++++++++-------------------------
 1 file changed, 9 insertions(+), 25 deletions(-)

(limited to 'src/top.v')

diff --git a/src/top.v b/src/top.v
index 37e33d7..e5a6381 100644
--- a/src/top.v
+++ b/src/top.v
@@ -1,36 +1,20 @@
 module top (
 	input clk,
 	input key
-	//output [5:0] led
 );
 
-wire rst;
-assign rst = ~key;
+wire rstn, clk_cpu;
+assign rstn = key;
 
-cpu cpu (
-  .clk(clk),
-  .rst(rst)
+clock_divider #(.N(1024 * 1024)) clkdiv (
+    .clk(clk),
+    .reset(!rstn),
+    .clk_out(clk_cpu)
 );
 
-/*
-
-reg [5:0] ctr_q;
-wire [5:0] ctr_d;
-wire clk_slow;
-assign reset = ~key;
-
-clock_divider #(.N(10000000)) clk_div (
-  .clk(clk),
-  .clk_out(clk_slow),
-  .reset(reset)
+cpu cpu (
+  .clk(clk_cpu),
+  .rstn(rstn)
 );
 
-always @(posedge clk_slow) begin
-	if (key) ctr_q <= ctr_d;
-	else ctr_q <= 6'b0;
-end
-
-assign ctr_d = ctr_q + 6'b1;
-assign led = ~ctr_q;
-*/
 endmodule
-- 
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