From 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Mon, 13 May 2024 07:46:45 +0200 Subject: refactoring, runs now on fpga --- src/top.v | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'src/top.v') diff --git a/src/top.v b/src/top.v index e5a6381..36ce912 100644 --- a/src/top.v +++ b/src/top.v @@ -1,20 +1,27 @@ module top ( input clk, - input key + input key, + output [5:0] led ); wire rstn, clk_cpu; assign rstn = key; +wire [31:0] dbg_t6; clock_divider #(.N(1024 * 1024)) clkdiv ( .clk(clk), - .reset(!rstn), - .clk_out(clk_cpu) + .rstn(rstn), + .clk_div(clk_cpu) ); +assign led[0] = ~clk_cpu; +assign led[5:1] = ~dbg_t6[4:0]; + + cpu cpu ( .clk(clk_cpu), - .rstn(rstn) + .rstn(rstn), + .dbg_t6(dbg_t6) ); endmodule -- cgit v1.2.3