From 008059fbe4e960a10bb4c444013129e0aaa02818 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 9 May 2024 11:26:33 +0200 Subject: stopped initializing ram and register file to 0 at beginning --- src/register_file.v | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'src/register_file.v') diff --git a/src/register_file.v b/src/register_file.v index 58ba061..11c36fe 100644 --- a/src/register_file.v +++ b/src/register_file.v @@ -8,6 +8,7 @@ module register_file ( reg [31:0] registers[31:1]; +// For debugging purposes: wire [31:0] reg_x0_zero, reg_x1_ra, reg_x2_sp, @@ -75,18 +76,18 @@ assign reg_x30_t5 = registers[30]; assign reg_x31_t6 = registers[31]; -integer i; -always @(posedge clk or rst) begin - if (rst) begin - for (i = 1; i < 32; i = i + 1) - registers[i] <= 32'b0; - end else begin +// integer i; +always @(posedge clk /*or rst*/) begin +// if (rst) begin +// for (i = 1; i < 32; i = i + 1) +// registers[i] <= 32'b0; +// end else begin rs1_data = (rs1 == 0) ? 32'b0 : registers[rs1]; rs2_data = (rs2 == 0) ? 32'b0 : registers[rs2]; if (we && (rd != 0)) begin registers[rd] <= rd_data; end - end +// end end endmodule -- cgit v1.2.3