From d107f7e40f02a7374b8685ba310500a6c38d43b1 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Tue, 14 May 2024 10:38:47 +0200 Subject: bug fixes --- src/alu_a_src_mux.v | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/alu_a_src_mux.v') diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v index 208cc82..8998b55 100644 --- a/src/alu_a_src_mux.v +++ b/src/alu_a_src_mux.v @@ -2,8 +2,9 @@ module alu_a_src_mux ( input [31:0] src_pc, input [31:0] src_pc_buf, input [31:0] src_rd1_buf, + input [31:0] src_rd1, - input [1:0] alu_a_src, + input [2:0] alu_a_src, output reg [31:0] alu_a ); @@ -12,11 +13,12 @@ module alu_a_src_mux ( always @(*) begin case (alu_a_src) - ALU_A_SRC_PC: alu_a <= src_pc; - ALU_A_SRC_PC_BUF: alu_a <= src_pc_buf; - ALU_A_SRC_RD1_BUF: alu_a <= src_rd1_buf; - ALU_A_SRC_0: alu_a <= 32'b0; - default: alu_a <= 32'b0; + ALU_A_SRC_PC: alu_a = src_pc; + ALU_A_SRC_PC_BUF: alu_a = src_pc_buf; + ALU_A_SRC_RD1_BUF: alu_a = src_rd1_buf; + ALU_A_SRC_RD1: alu_a = src_rd1; + ALU_A_SRC_0: alu_a = 32'b0; + default: alu_a = 32'b0; endcase end -- cgit v1.2.3