From deb7d0a6fc76d5250c238d479cf97d4755abef01 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sun, 12 May 2024 21:27:41 +0200 Subject: refactoring --- sim/testbench_cpu.v | 4 ++-- sim/testbench_register_file.v | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'sim') diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v index 2a2e185..d6c3975 100644 --- a/sim/testbench_cpu.v +++ b/sim/testbench_cpu.v @@ -5,9 +5,9 @@ module testbench_register_file(); reg clk; reg rst; -cpu uut ( +cpu cpu ( .clk(clk), - .rst(rst) + .rstn(!rst) ); integer file, r, eof; diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v index b0e0860..c1ca542 100644 --- a/sim/testbench_register_file.v +++ b/sim/testbench_register_file.v @@ -12,14 +12,14 @@ wire [31:0] data_rs0, data_rs1; register_file uut ( .clk(clk), - .rst(rst), + .rstn(!rst), .we(we), - .rs1(addr_rs0), - .rs2(addr_rs1), - .rd(addr_rd2), - .rs1_data(data_rs0), - .rs2_data(data_rs1), - .rd_data(data_rd2) + .ra1(addr_rs0), + .ra2(addr_rs1), + .wa3(addr_rd2), + .rd1(data_rs0), + .rd2(data_rs1), + .wd3(data_rd2) ); integer file, r, eof; -- cgit v1.2.3