From 7addab23add21dcb94bab5525787d1b97b11ce39 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 27 Apr 2024 14:27:10 +0200 Subject: simulation --- sim/testbench.v | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 sim/testbench.v (limited to 'sim') diff --git a/sim/testbench.v b/sim/testbench.v new file mode 100644 index 0000000..6221b01 --- /dev/null +++ b/sim/testbench.v @@ -0,0 +1,26 @@ +module testbench; + + reg reset = 0; + initial begin + $dumpfile("testbench.vcd"); + $dumpvars(0,testbench); + + # 17 reset = 1; + # 11 reset = 0; + # 29 reset = 1; + # 5 reset = 0; + # 128 $finish; + end + + reg clk = 0; + always #1 clk = !clk; + + wire [5:0] led; + wire reset_inv; + assign reset_inv = ~reset; + top blinky(.clk(clk), .key(reset_inv), .led(led)); + + initial + $monitor("At time %t, value = %h (%0d)", $time, led, led); + +endmodule -- cgit v1.2.3