From 2a3951a25ffe28342177e29cf97125ed89ca59a4 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Wed, 1 May 2024 16:47:56 +0200 Subject: added make target for testvec generation --- sim/testbench.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sim') diff --git a/sim/testbench.v b/sim/testbench.v index 33362d7..5a47111 100644 --- a/sim/testbench.v +++ b/sim/testbench.v @@ -25,7 +25,7 @@ module testbench(); reg [103:0] testvec [0:9999]; initial begin - $readmemh("../testvecs/alu_testvec.txt", testvec); + $readmemh("alu_testvec.txt", testvec); error_count = 0; vector_count = 0; end -- cgit v1.2.3