From 008059fbe4e960a10bb4c444013129e0aaa02818 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 9 May 2024 11:26:33 +0200 Subject: stopped initializing ram and register file to 0 at beginning --- sim/testbench_register_file.v | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'sim') diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v index a22f3e1..b0e0860 100644 --- a/sim/testbench_register_file.v +++ b/sim/testbench_register_file.v @@ -33,6 +33,7 @@ always #5 clk = ~clk; reg [1023:0] testvec_filename; reg [1023:0] waveform_filename; +integer i; initial begin if ($value$plusargs("testvec=%s", testvec_filename)) begin end else begin @@ -69,6 +70,14 @@ initial begin @(posedge clk); rst = 0; + for (i = 0; i < 32; i = i + 1) begin + we = 1; + addr_rd2 = i; + data_rd2 = 32'b0; + @(posedge clk); + #1; + end + file = $fopen(testvec_filename, "r"); if (file == 0) begin $display("ERROR: failed to open testvec"); -- cgit v1.2.3