From c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 23 May 2024 07:04:37 +0200 Subject: align --- rtl/src/clock_divider.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'rtl/src/clock_divider.v') diff --git a/rtl/src/clock_divider.v b/rtl/src/clock_divider.v index e673a43..8d25fdf 100644 --- a/rtl/src/clock_divider.v +++ b/rtl/src/clock_divider.v @@ -3,10 +3,10 @@ // to decrease its frequency, useful for debugging for example. module clock_divider #( - parameter N = 2 + parameter N = 2 )( - input clk, - input rstn, + input clk, + input rstn, output reg clk_div ); @@ -15,8 +15,8 @@ reg [31:0] counter = 0; always @(posedge clk or negedge rstn) begin if (!rstn) begin - counter <= 0; - clk_div <= 0; + counter <= 0; + clk_div <= 0; end else begin if (counter == (N-1)/2) begin clk_div <= ~clk_div; -- cgit v1.2.3